# AMD to broaden and specialize EPYC CPUs, already working on Zen 7 architecture — increased customization to better address evolving AI and cloud needs — retained record

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source: [news](https://highsignal.app/data/news) (news:toms-hardware)  published 2026-05-06 13:11 ingested 2026-05-07 08:18

[original source ↗](https://www.tomshardware.com/pc-components/cpus/amd-to-broaden-and-specialize-epyc-cpus-already-working-on-zen-7-architecture-increased-customization-to-better-address-evolving-ai-and-cloud-needs)

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AMD to broaden and specialize EPYC CPUs, already working on Zen 7 architecture — increased customization to better address evolving AI and cloud needs
AMD pursues segmented strategy for EPYC to address thread from custom CPUs.
Modern data center workloads are very diverse, and so are the requirements of data center operators for their hardware, which is why virtually all hyperscale cloud service providers nowadays have their own custom silicon programs. In a bid to stay competitive in the coming years, AMD plans to expand its portfolio of CPUs for data centers that will be targeted at different workloads.
With the Zen 4-based 4th Generation EPYC family, AMD offers a variety of processors SKUs aimed at AI, cloud, enterprise, network/edge, and small business/hosted service providers. But with Zen 5, the family is somewhat narrower. AMD's messaging today suggests that the company is moving toward more segmented EPYC products, including workload-specific SKUs, potentially different core/cache/interconnect configurations, and CPUs tailored for inference clusters, orchestration, low-latency AI tasks, and GPU-heavy deployments. Specifically, Su also hinted that this expansion is going beyond Venice, which includes Zen 7 and probably Zen 8 microarchitectures.
"We are working with customers right now on beyond Venice and what we are doing in those architectures," Su said.
Article continues below"[The industry] is going to need a broad portfolio of CPUs, not all CPUs are the same," said Lisa Su, chief executive and chairman of AMD, during the company's earnings call with financial analysts and investors. "Frankly, you are going to need different CPUs for whether you are talking about general purpose operations or you are talking about head nodes or you are talking about agentic AI tasks."
During the Q&A, Su repeatedly emphasized that AMD no longer sees server CPUs as a single homogeneous category. Instead, the company now views the market as split into multiple workload-specific segments, including general-purpose compute, CPU head nodes for accelerators, and CPUs optimized for agentic AI workloads. However, AMD plans to offer differentiation even within these categories to address the particular needs of its customers more precisely.
"What we have been focused on is building, not just one type, but […] throughput optimized, power optimized, cost optimized, and AI infrastructure optimized [models] as we have done in the Venice family," Su said.
Indeed, when it comes to AMD's 6th Generation EPYC processors based on the Zen 6 microarchitecture, the company plans to offer its codenamed Venice CPU with up to 256 cores for general-purpose servers as well as codenamed Verona processors for AI infrastructure (previously, AMD only introduced Verano CPUs as the processor that will power its next-generation rack-scale AI solutions). We yet have to learn whether CPUs aimed at agentic AI workloads will use separate silicon configurations or will re-use what was originally intended for general-purpose servers, but with different clocks or cache configurations.
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" The Venice family spans a broad set of CPUs optimized for throughput, performance per watt, and performance per dollar, including Verona, our first EPYC CPU purpose-built for AI infrastructure," Su said.
Considering the fact that AMD now expects the server CPU total available market to grow at a 35% compound annual growth rate and reach $120 billion by 2030, development of specialized models may be well justified even though CPU development in general and CPU implementation on leading-edge nodes in particular has become especially expensive in recent years.
So, while AMD did not formally announce any new CPU categories, its chief executive clearly signaled an ongoing expansion and specialization of EPYC offerings around AI infrastructure and other segments of the market.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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GenericUser2001 From the consumer side of things hopefully some of the specialization for different server workloads has a fair bit of crossover for everyday tasks. For example, the 3d cache on the x3d chips was originally intended for certain server workloads, but turned out to be really good for gaming too.Reply -
DS426 Reply
Not disagreeing, but the GPU is the bottleneck in gaming, not the CPU. To your point, 3D cache put AMD's CPU's on top in gaming, and now they just need that 3D cache moment with GPU's. They don't even have to beat nVidia at the very top end, but a strong high-end performer for hundreds less is what many are craving.GenericUser2001 said:From the consumer side of things hopefully some of the specialization for different server workloads has a fair bit of crossover for everyday tasks. For example, the 3d cache on the x3d chips was originally intended for certain server workloads, but turned out to be really good for gaming too. -
usertests There are tons of options on the table with multiple types of chiplets available. They are apparently going to use multiple I/O chiplets to control how many channels/lanes can be offered. There's supposed to be a 36-core Zen 7 chiplet with L3 cache disaggregated from it (related to but distinct from X3D). Maybe they can mix 8-core, 16-core, and 36-cores at will. Possibly add a graphics chiplet like the MI300A. It could get dizzying.Reply
If they don't want to offer dozens upon dozens of SKUs, they could allow the big hyperscaler/AI customers to customize their Epyc to the extent possible. -
bit_user Reply
To the extent that the CPU is still a bottleneck in gaming, Chips & Cheese found that Zen 5 is predominantly front-end bound on the 3 games they analyzed. If Zen 6 improves front-end throughput (which I think is consistent with the rumors?), then it could actually make a pretty big dent in what CPU bottlenecks remain.DS426 said:Not disagreeing, but the GPU is the bottleneck in gaming, not the CPU.
Source: https://chipsandcheese.com/p/running-gaming-workloads-through
The first big step towards that was RDNA 2's Infinity Cache. RDNA 3 was rumored to have bumps for stacking a cache die atop the MCDs, but it never happened for either market or technical reasons.DS426 said:To your point, 3D cache put AMD's CPU's on top in gaming, and now they just need that 3D cache moment with GPU's.
RDNA 4 had a canceled flagship that was rumored to make even more aggressive use of die stacking. I think we might yet see them implement that vision, but no guesses as to whether it'll happen in RDNA 5. -
usertests Reply
Based on MLID leaks, they could be ditching Infinity Cache (L3) entirely in favor of embiggened L2 cache, closer to what Nvidia uses. And no die stacking detected, but GPU chiplets that can be shared between mobile APUs, gaming dGPUs, the Xbox Helix, and workstation/accelerators.bit_user said:RDNA 4 had a canceled flagship that was rumored to make even more aggressive use of die stacking. I think we might yet see them implement that vision, but no guesses as to whether it'll happen in RDNA 5.
AT4 = 24 CUs, 10 MiB L2 cache (128-bit Medusa Halo Mini)
AT2/AT3? = 44-64 CUs, 16-24 MiB L2 cache (256/384-bit Medusa Halo with 48 CUs, 20 MiB L2)
AT0 = 138-184 CUs, 40-64 MiB L2 cache
I'm using these two leaks. There are some discrepancies (more than I remembered!) which I attempted to resolve above.
uLsykckkoZU:860View: https://youtu.be/uLsykckkoZU?t=860 (July 2025)
https://www.reddit.com/r/pcmasterrace/comments/1mydfvj/leaks_of_rdna5_new_gpus_coming_in_2027_possible/
K0B08iCFgkk:1183View: https://youtu.be/K0B08iCFgkk?t=1183 (August 2025)
https://www.notebookcheck.net/Next-gen-AMD-RDNA-5-desktop-GPUs-leak-Mid-range-AT3-GPU-features-48-CUs-and-massive-384-bit-bus.1093904.0.html
It remains to be seen how discrete desktop GPUs would handle these changes, but they should be great for Medusa Halo Mini, which is presumed to be the Strix Point successor. Strix Point has only 2 MiB L2 cache for graphics, while Panther Lake has a gigantic 16 MiB.
AT4 was estimated as having RTX 3060-4060 raster performance, while using at least 12 GB of cheap LPDDR5X. It could be made into a good dGPU for the low-end.
AT0 could allow an effective RTX 6090 competitor. But don't hold your breath.

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