# SK Hynix integrating cooling into next-gen high-bandwidth memory chips — retained record

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source: [news](https://highsignal.app/data/news) (news:blocksandfiles)  published 2026-05-26 10:15 ingested 2026-05-27 09:10

[Etched AI](https://highsignal.app/entities/ETCHED)[original source ↗](https://www.blocksandfiles.com/architecture/2026/05/26/sk-hynix-integrating-cooling-into-next-gen-high-bandwidth-memory-chips/5246039)

## extract

architecture
SK Hynix integrating cooling into next-gen high-bandwidth memory chips
High-bandwidth memory (HBM) manufacturer SK Hynix has devized a way to integrate cooling elements directly into its HBM chips to enable stable ops as die temperature rises.
HBM involves a stack of memory dies fastened to an interposer via a base logic die, which provides a high bandwidth path connecting them to a GPU.
Typically, Hynix says, a cold plate would be affixed to the top of the HBM die stack, indirectly drawing heat away from the stack. Instead, it puts an Integrated Cooling Element (ICE) in the area where the HBM dies link to the base die, the die-to-die physical layer (D2D PHY), which is where, it says, the heat is concentrated. The ICE column then connects to a cold plate and so draws heat more effectively away from the HBM stack.
The ICE element does not conduct electricity and it can be added to Hynix’ existing wafer level packaging process used to make HBM chips. Hynix says it’s also compatible with GPU manufacturers’ System-in-Package (SIP) architectures.
SK Hynix says its ICE tech “helps reduce thermal resistance by 30 percent and enables chips to operate stably even in high-temperature and high-pressure conditions.” This iHBM (ICE-HBM) approach is set to be used in the company’s HBM 5 chips which operate at higher speeds than current HBM 4 designs.
The thermal resistance idea is that the ICE enables heat to move up to the cold plate from the D2D PHY area 30 percent better than having it move unaided through the stacked HBM dies. This means the HBM die stack runs cooler and so enables it to operate faster and/or have more layers.
Kangwook Lee, SVP and Head of PKG Development at SK hynix, said: “iHBM is an optimal solution for thermal management, combining our memory design capabilities with advanced packaging technology.”
SK Hynix has not said where and how many ICE columns might be etched into an HBM die stack.
Bootnote
Here is SK Hynix’ acronym explainer:
- D2D PHY (Die-to-Die Physical Layer): a hardware interface that enables fast data transfer between the HBM base die and AI accelerator.
- ICE (Integrated Cooling Elements): A cooling element made of electrically non-conductive, thermally conductive silicon-based material, designed to dissipate heat from the HBM package by providing an additional thermal path.
- MR-MUF (Mass Reflow Molded Underfill): A process used for stacking semiconductors by injecting liquid protective materials between chips to protect circuits.
- Power Density: the amount of heat emitting per space serving as a key defining factor for the cooling efficiency and product lifespan.
- SiP (System in Package): A packaging technology that allows different chips to operate cohesively as a one system by placing them next to each other in a vertical or horizontal alignment.
- WLP (Wafer Level Packaging): The technology enables the packaging process and testing all at once without cutting a wafer into separate chips. It helps minimize the size of chips and improve electrical efficiency.

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