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Off the Wire Press Releases A PCIe/CXL device under test keeps its native generation, lane width and timing; the FPGA side runs full-rate SerDes. Plug-and-play prototyping and emulation. SANTA CLARA, Calif., Sept. 16, 2026 — SignatureIP, a pioneer and next-generation scalable Silicon Infrastructure Solutions provider, has announced MesoLink, its new Mesochronous Connectivity Bridge IP core that sits between a PCIe/CXL Device Under Test (DUT) and the FPGA SerDes in system-level verification, emulation and prototyping environments. The announcement was made at AI Infra Summit 2026, being held September 15–17 at the Santa Clara Convention Center. FPGA-based prototyping and emulation platforms routinely need to run the system side of a design at the host speed and lane width while the PCIe/CXL DUT operates at its own supported generation and lane width that meets FPGA timing. Reconciling the two has traditionally meant custom bridging logic, fragile clock-domain workarounds, and lengthy bring-up cycles. SignatureIP’s MesoLink is designed to remove that burden. MesoLink runs at the system’s native speed and lane width on one side, while independently interfacing to the DUT at whatever PCIe generation, lane width and FPGA timing the DUT supports on the other — translating seamlessly between the two domains. This allows the DUT to communicate with the system with no loss of continuity at DUT-side clock rates as low as 1 MHz, giving verification teams the flexibility to bring up, debug, and validate DUTs across a wide range of operating speeds without redesigning the surrounding test infrastructure. The IP is built around three interfaces: - System Interface: Connects to the host/system at system speed and lane width. - DUT Interface: Connects to the PCIe/CXL DUT using either a standard PIPE SerDes or the original PIPE interface. The DUT side supports PCIe Gen1 through Gen6 with all valid lane width options, x16/x8/x4/x2/x1, enabling seamless integration across a broad range of DUTs. - Configuration/Register Interface: A lightweight control and status interface that allows the host software configure speed and lane-width parameters and monitor bridge and link status. MesoLink’s timing-agnostic architecture also extends its usage well beyond FPGA-based prototyping and emulation. Because MesoLink absorbs the difference between system speed and DUT timing inside the IP itself, it is equally attractive for custom silicon designs — letting design teams tape out at the best possible timing for their own silicon rather than constrain that timing to match a fixed system requirement. “Verification teams have long had to choose between matching a fixed system speed or building custom bridging logic to work around it. MesoLink removes that trade-off — absorbing the timing difference inside the IP so every DUT runs at its own best speed, from FPGA bring-up through custom silicon tapeout. As PCIe and CXL scale to keep pace with AI infrastructure, that kind of timing freedom is exactly what our customers need,” said Purna Mohanty, CEO of SignatureIP. SignatureIP will showcase a live demo of its complete PCIe/CXL solution — including the new MesoLink — at its booth 001 – Level 01, Start Up Zone throughout AI Infra Summit 2026, September 15–17 at the Santa Clara Convention Center, developed in collaboration with ecosystem partners Siemens HAV and Teledyne LeCroy. The demo will show a PCIe/CXL DUT running at its native generation and lane width while seamlessly connected to a system running at full FPGA SerDes speed, illustrating MesoLink in action. MesoLink is offered as Soft IP, delivered as synthesizable RTL, and is also available as a fully integrated package for Siemens proFPGA CS platforms. The IP is available now for licensing; for more information or to schedule a meeting at the show, visit www.signatureip.ai or contact SignatureIP directly. About SignatureIP SignatureIP is the pioneer of next-generation silicon infrastructure IPs and Solutions. Founded in 2021, the company develops advanced Network-on-Chip and connectivity IP forming the basis for complete SoC platform designs, including PCIe, CXL, Ethernet and NoC IP, alongside custom Compute Subsystem, Memory Subsystem and IO Subsystem chiplet design services. SignatureIP’s leadership team brings 120+ person-years of engineering expertise in interconnect, networking, data center, storage, and connectivity IP, and the company has delivered 32+ successful SoC projects with engineering operations across the US, India, Singapore, and the Philippines. SignatureIP achieved PCI-SIG PCIe 5.0 certification in September 2025 and is headquartered in Milpitas, California. For more information, visit www.signatureip.ai. Source: SignatureIP
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