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Micron plans to use wafer bonding and High-NA EUV for next-gen DRAM — company also developing vertical high-bandwidth memory and vertical edge inference memory integrated directly on top of processors Put memory on top of processors too. Having jettisoned 4F2 memory cells from its roadmap, Micron must use different methods to continue scaling its DRAM devices in the coming years to keep up with rivals planning to use smaller DRAM transistors towards the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors. "DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view." Wafer bonding, High-NA EUV, and new materials Micron's current 1γ DRAM process is already in high-volume manufacturing, whereas its successor, 1δ, is scheduled to enter volume production in the second half of 2027. The latter promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond 1δ, Micron plans to introduce wafer bonding with its 1ε process, which is currently under development. However, the company has not disclosed how it intends to implement wafer bonding or what improvements it expects from the technology. For subsequent generations — ζÅ and ηÅ — Micron plans to adopt High-NA EUV lithography (ζÅ, zeta angstrom, Micron's 1st Generation sub-10nm-class DRAM node) and new materials (ηÅ, eta angstrom, Micron's 2nd Generation sub-10nm-class DRAM node) to continue shrinking DRAM cells. For many of its upcoming fabrication technologies that will be used over the next five to 10 years, Micron is also collaborating with Albany NanoTech. Of course, as with all organizations like Albany NanoTech, we are mostly talking about fundamental, or pre-competitive, IP that could be used for DRAM production at some point. "Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM," said DeBoer. "In particular at Albany with our team there, focused on the next five to ten years." Micron is also developing 3D DRAM technologies and lists two generations — 3D1 and 3D2 — in its roadmap already. However, the company has not disclosed its architectures or launch schedules, as it intends to introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing costs, complexity, and performance over conventional planar DRAM. "When we look at three 3D DRAM we have that on the roadmap, as I mentioned, and it is shown here in between one zeta and one eta," said Micron's CTO. "But in reality, this is a parallel path, and we will implement it [3D DRAM] in a fashion that is ideal for cost, complexity, and device performance." Get Tom's Hardware's best news and in-depth reviews, straight to your inbox. Going vertical, becoming critical Beyond developing new process technologies for its upcoming DRAM products, Micron is also working on all-new types of DRAM products that are tailored for very specific use cases, including vertical HBM (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations. vHBM will place memory stacks directly on top of processors (such as AI accelerators and AI GPUs) rather than next to them. This approach promises substantially lower latencies and higher bandwidth thanks to shorter connections. However, placing memory above a processor creates significant thermal challenges and limits the number of memory stacks that can be integrated on top of an ASIC. Therefore, Micron expects vHBM to complement conventional HBM, which will continue to provide the bulk of memory capacity in many AI accelerators. Another technology under development is vertical edge inference memory (vEIM), which shares architectural and packaging characteristics with vHBM but targets different applications. Whereas vHBM prioritizes maximum bandwidth for high-performance AI accelerators, vEIM is focused on energy efficiency for edge AI processors used in autonomous vehicles, robotics, and other power-constrained devices. Nonetheless, even the 1st Generation vEIM targets formidable 2 TB/s bandwidth at <1pJ/bit energy, which is in line with what HBM4 currently offers (at 8 GT/s over a 2,048-bit interface). Micron intends to optimize these products with customers according to their bandwidth, capacity, and power requirements. Both vertical memory architectures will require advanced packaging technologies, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management will also be critical, especially for vHBM. To meet cooling requirements, Micron is developing specialized heat-spreading structures to transfer heat from hot regions of memory base dies through the DRAM stacks. The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. What is important about the development of such types of memory is that it indicates that future improvements in memory performance will increasingly depend on advanced packaging and closer integration with processors, which will require collaboration between DRAM makers and logic developers. In turn, this transforms memory from a commodity to a critically important ingredient of an ASIC design. Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds. Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. - alan.campbell99 Doesn't look to me like this is anything consumers will see, but then the consumer is no longer their focus.Reply - usertests alan.campbell99 said:Doesn't look to me like this is anything consumers will see, but then the consumer is no longer their focus.All of these developments should increase density: Micron's current 1γ DRAM process is already in high-volume manufacturing, whereas its successor, 1δ, is scheduled to enter volume production in the second half of 2027. The latter promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond 1δ, Micron plans to introduce wafer bonding with its 1ε process, which is currently under development. Which should lower the cost per bit (of manufacturing). Then we'll see 3D DRAM at some point in the 2030s: it intends to introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing costs, complexity, and performance over conventional planar DRAM. These developments will lower cost per bit, at least before supply/demand is taken into account. I believe we'll see $1/GB, and even $0.10/GB for the latest memory eventually, and consumer devices with at least 16x the memory per tier. For example, today's 8 GB MacBook Neo equivalent gets 128 GB... maybe in 2040. The only obvious reason to have that much memory in basic devices is on-device AI. 3D DRAM is how we'll get there. 3D NAND improved cost per bit by around 10x within a decade of being on the market. Reply - thestryker alan.campbell99 said:Doesn't look to me like this is anything consumers will see, but then the consumer is no longer their focus.Standard node improvements will filter down and if there's any consumer benefit from the current ai disaster it's that these should filter through sooner. Since supply is the source of the problem all NAND/DRAM that can be used will be which should mean less older for making consumer parts. I would expect to see some density benefits appear as well as older products on older nodes get retired. There are currently three sizes of DDR5 for example (16Gb, 24Gb, and 32Gb) but the spec allows for up to 64Gb so if there are additional capacity breakthroughs we could see the 16Gb potentially effectively retired. usertests said:Which should lower the cost per bit (of manufacturing).It will, but I wouldn't expect to see any that to be reflected in buyer prices unless ai demand collapses. The manufacturing cost improvements are pretty low and the historical market has been low margin so supply and demand has controlled things more than manufacturing cost. usertests said:3D DRAM is how we'll get there. 3D NAND improved cost per bit by around 10x within a decade of being on the market.I'm not quite as bullish on 3D DRAM at the consumer level as you are, but it definitely has the potential to change the DRAM. industry. I think it's largely going to be used for enterprise to squeeze out density since they can charge a lot more to double capacity per channel for example. It will probably be the eventuality for all DRAM assuming a new technology doesn't happen in the meantime though. Reply
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