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China crafts working 3nm gate-all-around transistors without EUV — stacked nanosheets target 3nm without EUV, but full node remains distant But China's 3nm remains years away. The Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has developed an experimental process flow for building stacked-nanosheet gate-all-around (GAA) transistors using immersion DUV lithography and demonstrated functional devices. The flow is intended for eventual use with 3nm-class and smaller process technologies by Chinese chipmakers that do not have access to EUV scanners, reports DigiTimes. While IMECAS has demonstrated functional GAA devices, it has not disclosed the critical geometrical parameters that would allow comparisons to 3nm-class transistors from other chipmakers. Furthermore, the experimental process flow for building transistors is not even a defined process flow for building research chips, much less a complete 3nm-class manufacturing process. Nonetheless, the achievement is quite important as it demonstrates that China is capable of developing its own branch of semiconductor evolution without using leading-edge tools from Western companies. Early process integration complete Ye Tianchun, chief engineer of China's National Major Special Project 02, said at the IC World conference in Beijing that IMECAS had completed 'early process integration' for stacked nanosheet-channel GAA transistors fabricated with DUV lithography. The researchers from IMECAS obtained devices with Ion/Ioff ratios of 9.7×10⁵ and 7.6×10⁵, both exceeding the 5×10⁵ threshold, which means gate control of the stacked sheets is working. These figures indicate that the experimental transistors can distinguish between their conducting and non-conducting states, but they say little about transistor density or whether their physical dimensions correspond to those expected from commercial 3nm-class technologies. In particular, IMECAS has not disclosed gate pitch, metal pitch, nanosheet dimensions, transistor density, SRAM density, or other geometrical characteristics that could put its devices into perspective against 3nm-class production nodes from Intel, Samsung Foundry, or TSMC. Therefore, the achievement should be viewed as validation of a stacked-nanosheet GAA process flow based on DUV lithography rather than evidence that China has developed a 3nm process without EUV. The most important part of the experiment is that IMECAS is investigating how GAA devices intended for future 3nm-class and more advanced technologies can be fabricated without using EUV lithography, something that nobody has done before in volume production. GAA transistors have succeeded FinFET devices at leading-edge nodes because placing the gate around nanosheet channels provides better electrostatic control as transistor dimensions shrink. IMECAS has been developing technologies required for this transition since 2020, and its particular focus was on nodes below 3nm, which is why it now mentions 3nm as part of its announcement. Get Tom's Hardware's best news and in-depth reviews, straight to your inbox. Reducing China's dependence on advanced foreign tools It goes without saying that IMECAS' work in recent years has been focused on reducing China's dependence on tools, software, and other technologies that are designed by Western companies and therefore subject to export restrictions imposed by American, Japanese, or European countries. Among other things, Ye mentioned architectural innovation, design-technology co-optimization (DTCO), system-technology co-optimization (STCO), and 'extracting more value' from mature fabrication technologies. For now, IMECAS' result demonstrates a DUV-based route for researching stacked-nanosheet GAA transistors intended for future 3nm-class technologies, but not a China-developed 3nm process ready for manufacturing even in the long-term future. Even if IMECAS eventually demonstrates appropriately scaled GAA devices using DUV, or discloses critical geometry parameters of the current work, this would still be far from a production-ready 3nm-class technology. Commercial manufacturing requires integration of lithography with deposition, etching, cleaning, metrology, process control, materials, temperatures, and many other steps and parameters. For now, IMECAS has not demonstrated such a manufacturing flow. Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds. Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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