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Micron skipping planned NAND generation Micron is accelerating its planned 3D-NAND technology roadmap by jumping a generation to provide additional die capacity, speed and energy efficiency faster. The company is currently shipping G9, its ninth generation, with 276 layers. The first product using this tech, the 2650 client SSD, was launched in July 2024. Micron held a Technology and product webinar on its Investor Relations website on October 21. Its President and Chief Technology and Products Officer Scott DeBoer discussed Micron's technology foundation, multigenerational roadmap, customer co-design, and long-term research positions in DRAM, HBM, and NAND. DeBoer said in the NAND section: “We've been in a very strong position with our Gen 9 NAND, and this leadership is going to extend with Generation 11. And this is a significant leap. We have optimised this memory. We've actually gone back and ensured that this memory is optimised for the AI products of the future and intentionally, which is why it goes from Gen 9 to Gen 11. We've made substantial improvements that this node really brings relative to any prior NAND.” G11, compared to G9, has twice the bit density, an up to 1.5x increase in I/O speed and needs 25 percent less energy to transfer a bit. DeBoer said: “This G11 technology is the world's most advanced NAND. It will ramp in the second half of next year. Also, it's based on wafer on wafer bonding technology … We’ll be at more than 400 layers and we'll give more specifics on that next year closer to the launch date.” He also discussed future NAND product technologies that could use G11 3D NAND. One was a higher-speed SSD with smaller block sizes enabling much higher IOPS. The second was a higher bandwidth SSD, with stacked layers connected to a base die by through silicon vias (TSVs) like high-bandwidth memory (HBM), and similarly placed next to an accelerator processor (GPU). DeBoer said: “There's really two focus areas here. One is on high IOPS, AI class NAND, which is [an] SLC-based design implemented in small blocks to design ultra fast memory storage products. And this is a key piece that meets several emerging use cases noted here and really is a major focus for Micron in terms of getting these products out the market over the next couple years. On the other side of this architecture and design path is high bandwidth AI-class NAND focused on other emerging use cases. And these ultimately are more costly and have to be implemented in partnership with customers in a way to ensure that they're meeting the mark and the cost point to drive the value proposition.“ The high-bandwidth NAND would not be positioned along the accelerator’s shoreline like HBM, “as we don't think that has merit, but along closer positioning points to the compute itself to make use of this high performance NAND and the viability of that path.” He did not mention the very similar high-bandwidth flash (HBF) technology being promoted by Sandisk and SK Hynix. Both have stacked layers of 3D-NAND dies above a base logic or controller die and a connection to a nearby accelerator, possibly/probably by using an interposer. The high-IOPS SSD would be in the 25 - 100 million IOPS area while next-generation SSDS could hold up to 512 TB. Like the high-bandwidth AI-class NAND, the high-IOPS NAND would also be located close to the accelerator. DeBoer also mentioned future Micron AI-class NAND being used in AI PCs and workstations, automotive, robotics, mobile and wearable products. High-Bandwidth Memory BNP Paribas Equity Research senior analyst Karl Ackerman told subscribers that Micron's HBM roadmap runs through HBM6, with vHBM and vEIM starting production In 2028: "Micron noted that HBM4 36GB 12-high entered high-volume manufacturing in March 2026, and HBM4E is currently sampling with key customers. The company targets high-volume manufacturing of HBM4E in 2027, HBM5 in 2028, HBM5E in 2029, and HBM6 in 2030. "Additionally, Micron announced vertical HBM (vHBM), which places the DRAM stack directly on top of the processor rather than beside it, delivering greater bandwidth than conventional HBM. The trade-off is this inhibits the cooling of the processor, which is why we expect vHBM to be deployed in conjunction with traditional HBM. Meanwhile, vEIM (vertical edge inference memory) applies the same stacked structure to edge devices, placing low-power LPDDR on top of a logic die, and Micron’s first-generation vEIM targets 2TB/s of bandwidth at less than 1 pJ/bit (this approach is similar to what d-Matrix has pioneered). Both new lines are targeted for volume production in 2028 and have three generations on the roadmap through 2030." And: "Micron built the HBM4 base die on its own CMOS process, while competitors transitioned to foundry-made base dies. However, HBM4E’s speed and power targets require more advanced CMOS, so Micron is now moving to foundry-made base dies. HBM4E is also the first generation for which Micron offers custom HBM alongside the JEDEC-standard product, which we think includes Nvidia’s NVHBM. For custom parts, Micron and customers jointly design the base die, integrating the customer’s logic IP with Micron’s memory IP." Bootnote 1 Micron is starting to have a habit of skipping 3D NAND generations: - Gen 1 - 32 layers - Gen 2 -64 layers - Gen 3 - 96 layers - Gen 4 - 128 layers - Gen 5 - 176 layers - Gen 6 - 232 layers at end 2022 - branded G8 externally in Nov 2024 - Gen 7 - 276 layers - branded G9 externally - Gen 8 - planned 300+ layers, branded G10 externally but abandoned in Oct 2026 - Gen 9 - planned 400+layers, branded G11 externally Oct 2026. We think this is marketing-based and a response to Samsung having its V9, 10 and 11 generations, SK hynix with V9, 10 and 11 ditto, and Sandisk/Kioxia with their BiCS 9, 10 and 11. Bootnote 2 According to Imec, Wafer-on-wafer (WoW or W2W) bonding is a semiconductor 3D integration technique in which two (or more) fully processed silicon wafers are aligned and bonded together as complete wafers, after which the bonded stack is diced into individual multi-die chips.
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