Charting RISC-V’s Future in HPC

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There are more than 30 billion RISC-V cores deployed in the world, and some analysts estimate the open processor architecture will own a third of the market within five years. While the forecasted future for RISC-V is bright, the chip has so far failed to live up its billing in the HPC world. But that will likely change over the next few years as new RISC-V chips to market and ecosystem matures.
That’s the takeaway from a Birds of Feather session at the ISC 2026 conference last month. Titled “HPC Next: Reflections and Progress on the RISC-V Ecosystem,” the session featured RISC-V proponents who are confident that the chip’s best days are ahead.
“I think that owning both the hardware and software stack end-to-end is a huge attraction,” said Manolis Marazakis, a principal staff research scientist at the Institute of Computer Science-FORTH in Greece. “We can do really co-design the standards for the instruction set, but also extensions are open. And we can do extreme customization.”
This level of customization is not possible on X86, which is a closed architecture. Arm is more approachable as one can license an instruction set architecture (ISA), Marazakis said. We have seen numerous Arm-based supercomputers, including the current number one cluster on the TOP500 list, the new LineShine system. But Arm is controlled by a single vendor, the UK-based Arm Holdings.
That doesn’t mean that RISC-V is risk-free. It comes with caveats, Marazakis stated. “There has been a lot of development, but it remains to be proven, that the particular approach with open standards that include both instructions and stations will actually give us a tangible advantage,” he said. “We need the flagship….a lighthouse deployment, a large enough system to demonstrate all these components working in a good-enough way.”
For years, Arm was considered to the Switzerland of ISAs, and said they would never compete with their customers, said Dan Schecter, a principal engineer at NextSilicon, which recently announced plans to productive its Arbel RISC-V-based chip into a 64-core or 128-core enterprise-grade processor by 2028.
“I think it’s very clear that that statement is no longer true these days,” Schecter said. “I think that RISC-V, what it actually brings to the table is the fact that the ISA is a consortium. It’s a non-profit organization. It’s meant to actually become a real Switzerland of ISAs and ensure that there’s always competition.”
Schechter predicted that the RISC-V chip would become a credible entity in HIPC within the next three years. “In three years, I think you’ll see very interesting things.”
Another RISC-V chip company, Inspire Semiconductor, was represented at the BOF by Doug Norton, the company’s chief marketing officer. Norton noted that RISC-V chips are already widely deployed–they’re just not in the public eye.
“There’s a lot of enthusiasm for what we’re doing,” he said. “Nvidia and Google’s TPU have both taken out their microcontrollers of their own and ARM and put in RISC-V, so they’re shipping ridiculous numbers of cores of RISC-V. They’re just not front and center. They’re used for control.”
Norton noted that Inspire Semi is planning to ship by the end of the year its latest product, the Thunderbird, a PCI board with 6,144 RISC-V cores, delivering 24 teraflops of FP6
4 performance.
“That’s 24 times as many [cores] as you get from x86 or ARM,” Norton pointed out. “Of course they’re not general purpose. They’re lean, mean, low-power cores for compute, but very, very efficient.”
The Thunderbird is an HPC-first product that Inspire Semi hopes will fill the in void left by Nvidia, which is moving away from native FP64 performance with its latest GPU in favor of token generation for AI, Norton said.
“I think we’re going to have some good accelerated systems here pretty quick, including ours,” he said. “Will there be an all RISC-V [cluster]? Probably in five years. Two years? Maybe not.”
Teresa Cervero, a Barcelona Supercomputing Center research engineer and the vice chair of the RISC-V International Special Interest Group in HPC (SIG-HPC), says the best part of RISC-V is that it’s community driven.
“There is a common agreement between different people coming from industry, coming from academia, individuals that really want to make this happen,” she said. “One of the unique things of RISC-V is the velocity, the speed up of how many extensions have been approved or ratified during these years.”
The energy efficiency of RISC-V systems is one of the advantages, and that eventually could play a role in building greener HPC resources. “But this is not a magic ring that controls everything,” she said. “There is a set of challenges ahead.”
Cervero said she would like to see a RISC-V HPC system being deployed within three years that delivers the big performance gains that people are hoping for. “As far as having RISC-V IP and then new architectures and having exascale systems–where we are, we are close to this,” she said. “We are not there yet, but we have time. So we are moving faster.”
“What I’ve seen is that RISC-V ecosystem, the community, is gaining speed…and we are closing the gap with current systems,” Cervero continued. “We want to see really systems that are working, and we can access them and run our applications and get big performance comparable with what we have, or even better to what we have nowadays.”
Daniele Gregori, the chief scientific officer for E4 Computer Engineering, has experience deploying RISC-V systems, as he was involved in validating the software stack of the six-node Monte Cimone cluster that was deployed in 2021 at CINECA Computing Center at the University of Bologna in Italy.
The RISC-V software stack has improved considerably in recent years. “In the last version, we see a big improvement of the performance,” Gregori said. “Not comparable today with X86, but a very significant increase in just four years.”
Gregori, who is a physicist by training, said recent test runs using the codes for the multi-body problem in astrophysics showed a lot of promise for RISC-V. “We have an improvement of two times in terms of time-to-solution for this specific workload,” he said.
There is still a lot of work to do in terms of migrating scientific codes to run on RISC-V, Gregori said. That will help as more RISC-V systems become available and adoption beings to increase.
“Today we have a dedicated partition of HPC clusters in Europe with European technology based on RISC-V,” he said. “I think in five years we need to try to be more aggressive and think that should be possible to have also full system in production based on this technology in five years.”
When it comes to porting codes, there is always some work involved, no matter what platforms are involved Cervero said. Today, the RISC-V community is working on improving the tools to improve the performance of vector processing on RISC-V chips.
“Like everything, sometimes it works and sometimes it doesn’t work,” she said. “But with the vector agnostic with LLVM, there is no issue.”
The promise of no vendor lock-in with RISC-V is one of its biggest competitive advantages, especially compared to GPUs from Nvidia. While CUDA is well-liked and widely adopted by the HPC community, there’s no getting away from the lock-in that currently exists with CUDA, according to Norton.
“Fifteen years ago, when we started going down the GPU path with Nvidia, there was really nothing else. We all kind of knew it was a lock-in and we did it because that was the choice,” he said. “And now there’s a lot of people who really need to get out of that lock in. There’s going to be people who really don’t want this type of stuff. Openness is going to matter.”

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