AI infrastructure enters multi-architecture fabric competition; Optical-copper interconnects and supply-chain coordination determine system performance

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DIGITIMES observes that AI systems are moving from single-server setups to rack-level, multi-rack, and pod-level deployments, shifting the performance contest from compute chips to the broader AI fabric. Scale-up handles high-speed interconnects within nodes and racks, while scale-out links AI clusters through network interface cards (NICs)/DPUs and leaf-spine architecture. The full path spans PCIe (peripheral component interconnect express), switches, serializers/deserializers (SerDes), digital signal processors (DSPs), optical modules, cables, and connectors, creating a division of labor between short-reach copper interconnects and optical backbones for switches. As CSPs increasingly develop their own ASICs, the AI fabric is set to become more multi-architectural and customized, further expanding opportunities for high-speed I/O, optical communications, and Taiwanese suppliers across the physical interconnect supply chain.
As generative AI and large-model applications continue to expand, AI infrastructure is rapidly scaling to rack-level, multi-rack, and pod-level deployments. Recent launches by Nvidia, Advanced Micro Devices (AMD), and Alphabet's Google of Vera Rubin NVL72, Helios, and TPU Rack systems, respectively, show that AI racks are gradually becoming the basic deployment unit after integrating compute, memory, storage, and interconnect resources. As the number of accelerators and system scale keep growing, performance competition increasingly depends on fabric-based connections among different compute nodes and resources, making interconnect capability a key factor in system scalability and accelerator efficiency.
This report looks at the importance of AI Fabric, the vendor types that sell them, and the key components that will affect its deployment.

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