SC26: Announcing Best Paper and Best Student Paper Finalists

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Off the Wire Press Releases Aug. 18, 2026 — Each year, the SC Technical Papers program recognizes outstanding research through its Best Paper and Best Student Paper awards. To make this process more transparent, the following is an overview of how these papers are nominated, evaluated, and selected. The nomination process begins within each technical area. During the online review discussions and subsequent Program Committee meetings, reviewers and Area Chairs identify papers they believe merit consideration for the Best Paper or Best Student Paper awards. Each area may nominate papers in one or both categories. In some cases, a student-authored paper may be nominated for both Best Paper and Best Student Paper and may be a finalist in each category. Best Paper is selected first and takes precedence. As such, if a student-authored paper wins, it is no longer eligible for Best Student Paper. Candidates for the Best Student Paper award must be presented by a student author who made a significant intellectual contribution to the work. Because nominations are made independently within each area, an area-level nomination should not be interpreted as the strongest submission across the entire Technical Papers program. Instead, these nominations identify those papers that each technical area believes should advance for broader consideration. This approach gives every area the opportunity to highlight technically diverse papers with the greatest scientific merit. After the area-level nominations are complete, the nominated papers become finalists for the corresponding award. A separate committee of judges will evaluate the finalists during the conference. The judges remain anonymous until the Awards ceremony. This preserves the independence of the evaluation process and allows the committee to assess each finalist without external influence. Final award decisions will be based on two components: - Quality of the final published paper. - Quality and effectiveness of the conference presentation. The judging committee will complete its evaluation during the conference after attending the finalist presentations. They then consider both the written papers and presentations as part of the review. Following these deliberations, the Best Paper and Best Student Paper award winners will be announced during the SC26 Awards Ceremony. In addition to recognizing the winners, all finalist teams will be acknowledged for their outstanding contributions to the SC26 Technical Papers Program. The Nominees Are… Eligible for either Best Paper or Best Student Paper Sensor Placement for Tsunami Early Warning via Large-Scale Bayesian Optimal Experimental Design Sreeram Venkat, Omar Ghattas, Stefan Henneking, University of Texas at Austin, USA Real-time tsunami early warning relies on distributed sensor networks to infer seismic sources and seafloor motion. Optimizing these networks via Bayesian optimal experimental design (OED) is exceptionally challenging for systems governed by hyperbolic partial differential equations, which lack the spectral decay required by standard low-rank approximations. We present a scalable Bayesian OED framework for linear time-invariant systems. By reformulating the inverse problem in the data space, we transform OED into dense matrix subset selection. We propose a multi-GPU, Schur-complement-update-based, greedy algorithm that solves the OED problem using a pipelined approach that fully overlaps I/O with GPU computations. Our framework achieves near-perfect weak and strong scaling across hundreds of GPUs on Perlmutter and Frontier. Applied to the 2025 Gordon Bell Prize-winning digital twin for tsunami forecasting in the Cascadia Subduction Zone, we optimize a 175-sensor network, minimizing the uncertainty of a parameter field with over one billion degrees of freedom. Format-Driven Automatic Pipeline Construction and Load Balancing for SpMM on GPUs Kelun Lei, Hailong Yang, Kaige Zhang, Zhongzhi Luan, Kejie Ma, Tianyu Feng, Xin You, Yi Liu, Depei Qian, Da Huo, Beihang University, China Sparse Matrix-Dense Matrix Multiplication (SpMM) is critical for graph neural networks, yet GPU optimization faces challenges from irregular sparsity and load imbalance. Existing hand-tuned solutions tightly couple format design with kernel implementation, requiring complete reimplementation when the format changes. We present Sparsene, a format-driven automated framework that derives all kernel-level optimizations from a single sparse format specification. A hierarchical DSL decouples format structure from implementation via declarative blocking primitives and dynamic lowering transformations. The frontend compiles the DSL into a pGraph of fine-grained pTasks, whose granularity and dependencies are entirely determined by the format. This format-derived pGraph then drives both automatic pipeline construction, where a hardware-aware simulator and two-stage hybrid search identify high-quality pipeline plans, and format-aware load balancing, which selects among binding strategies to mitigate thread-block imbalance. Experiments on NVIDIA A100, H100, and RTX 4090 demonstrate up to 8× speedup over state-of-the-art solutions with strong performance portability. Every Microsecond Matters: Achieving Near Speed-of-Light Latency in GPU Collectives Torsten Hoefler, Siyuan Shen, Tiancheng Chen, ETH Zürich; Jeff R. Hammond, Anton Korzh, John Bachan, Nishank Chandawala, Kamil Iskra, Sylvain Jeaugey, Arnav Goel, Zhenhao He, NVIDIA GPU collective communication is often optimized for bandwidth, yet many emerging workloads are latency-bound. Long-context LLM inference is a key example, where small collectives lie on the critical path of token generation, making microsecond-scale overheads impactful. In this work, we study how to approach the hardware Speed-of-Light (SoL) lower bound for GPU collectives within a scale-up network. We identify key design principles, including barrier-free synchronization and efficient use of symmetric memory and multicast. Building on NCCL’s device-side API, we develop low-latency interfaces for constructing custom kernels and implement new symmetric collectives in NCCL. Microbenchmarks show substantial latency reductions, achieving within 10% of the measured SoL bound. Integrated into applications, these kernels reduce inter-token latency and improve throughput in LLM inference, while also accelerating cuSOLVERMp, demonstrating benefits across AI and HPC workloads. Best Student Paper Nominees Do We Need Tensor Cores for Stencil Computations? Qiqi Gu, Haibing Guan, Chenpeng Wu, Jianguo Yao, Shanghai Jiao Tong University, China; Heng Shi, Shanghai Enflame Intelligence Technologies Co. Ltd, China Stencil computation is a fundamental kernel in scientific computing, widely used in applications such as fluid dynamics and weather simulation. Although stencils are traditionally considered memory-bound and thus ill-suited for compute-oriented Tensor Cores, recent studies report substantial acceleration, creating an apparent contradiction. This paper resolves this discrepancy through a systematic performance analysis of stencil computations on Tensor Cores. We revisit stencil-to-Tensor-Core mappings, quantify the computational redundancy introduced by hardware-driven transformations, and develop an enhanced performance model that captures arithmetic-intensity shifts under temporal fusion. From this model, we derive analytical criteria that provide a first-order estimate of whether Tensor Cores will outperform, match, or underperform CUDA Cores for a given stencil and hardware setting. Our analysis identifies the performance sweet spot for Tensor Core acceleration. Evaluations on NVIDIA GPUs with state-of-the-art implementations, including EBISU, ConvStencil, and SPIDER, validate our criteria and show its value for guiding stencil optimization. DOLPHIN: Scalable Disk–RAM–GPU Pipelined Training for Massive Temporal GNNs Wenbo Zhen, Xike Xie, Rui Guo, Zezhong Ding, Junlin Lv, University of Science and Technology of China, China; Jianliang Xu, Hong Kong Baptist University, Hong Kong SAR Temporal graph neural networks (T-GNNs) play a key role in modeling dynamic graphs by learning representations that capture evolving structures and interactions. However, scaling T-GNNs remains challenging, as massive real-world graphs and complex temporal dependencies incur prohibitive runtime and memory costs. Existing systems often preload entire datasets into RAM and rely on RAM–GPU pipelines, suffering from batch-boundary pipeline bubbles, thereby limiting throughput. In this paper, we present DOLPHIN, a scalable Disk–RAM–GPU pipelined system for massive T-GNNs. DOLPHIN groups training batches into chunks and incorporates two key techniques: an I/O-efficient feature window scheduler for just-in-time Disk-to-RAM chunk provisioning, and a dependency-graph–based parallel execution plan that improves GPU utilization while preserving model quality. Together, these techniques improve pipeline efficiency across the Disk-RAM-GPU memory hierarchy and computation phases. Experiments on six real-world graphs show DOLPHIN delivers up to \textbf{21.07$\times$} faster training and reduces RAM usage by up to \textbf{92.04\%} compared to state-of-the-art baselines. Best Paper Nominees FSZ: Breaking the Prediction-Throughput Trade-off in GPU Lossy Compression Jiajun Huang, University of South Florida, USA Existing fast GPU error-bounded lossy compressors achieve high throughput but limited compression ratios because they use a fixed first-order predictor on independent blocks. We propose FSZ, which redesigns the prediction stage with three mutually reinforcing innovations within a single CUDA kernel: (1) cross-block prediction state carries Lorenzo prediction across block boundaries, eliminating 7 of 8 boundary residuals; (2) per-tile adaptive multi-order prediction and centering selects the best strategy per tile from first-order, second-order, and centering variants; and (3) single-pass four-way evaluation exploits a mathematical property of finite differences to evaluate all variants from a single data read. Experiments on NVIDIA GH200 with 8 real-world HPC datasets show that FSZ outperforms cuSZp-P by up to 10.95x and the state-of-the-art cuSZp-O by up to 2.92x in compression ratio, while simultaneously achieving the highest throughput (676 GB/s compression, 785 GB/s decompression) among all evaluated compressors. From Alert Fatigue to Root Cause: Causal Failure Cascade Discovery in HPC System Awais Khan, Christopher Zimmer, Anjus George, Ahmad Maroof Karimi, Feiyi Wang, Woong Shin, Oak Ridge National Laboratory, USA Production HPC systems generate massive volumes of heterogeneous logs that encode rich signals about failure propagation across hardware and software layers. In this paper, we present a framework for causal discovery in HPC logs that combines three complementary methods: Transformer-based counterfactual intervention, PCMCI+, and transfer-entropy. Because production environments lack labeled ground truth, our framework uses cross-method triangulation to assign confidence to discovered causal relationships. We further introduce an architecture-aware AI-agent that evaluates the physical plausibility of these relationships and enriches them with mechanism-level explanations, diagnostic commands, and severity assessments grounded in Frontier system documentation. We apply the framework to 18.4 billion log events from the Frontier supercomputer and construct a structured taxonomy of 87 event types spanning diverse hardware and software subsystems. Our results reveal causal relationships across HPC-subsystems, including rare failure pathways and multi-hop cascade chains. This work provides a scalable path toward architecture-grounded root-cause diagnosis in production HPC-systems. DySpin: A Plug-and-Play Library Advancing Dynamic Sparse Long-Context Inference Chengyu Sun, Dazhao Cheng, Yaqi Xia, Wuhan University, China; Xiaobo Zhou, University of Macau, China; Donglin Yang, NVIDIA Corporation, USA; Ruirui Pan, Central China Normal University, China We propose DySpin, a plug-and-play library designed to advance Dynamic Sparse long-context inference. DySpin introduces a training-free runtime allocation strategy that dynamically adjusts token budgets, preserving critical tokens that fixed-budget methods would otherwise discard, thereby improving model accuracy. To mitigate the attention kernel workload imbalance inherently caused by runtime allocation, we develop FastEstimate, a fused kernel that integrates token importance evaluation and selection to efficiently generate dynamic scheduling indices. These indices then guide a specialized decoding attention kernel, ensuring fine-grained, load-balanced computation. To tackle memory capacity constraints with accuracy preservation, DySpin incorporates 6-bit KV cache quantization. By enabling register-level parallel unpacking and dequantization through a novel packing format, DySpin significantly alleviates the severe dequantization overhead during attention computation. DySpin can be seamlessly integrated into existing sparse frameworks, delivering superior model accuracy and lower latency for long-context inference. SwarmLoRA: Batched Computation across Isolated Functions for Serverless LoRA Inference Mausam Basnet, Tong Shu, University of North Texas, USA Low-Rank Adaptation (LoRA) has produced over 100,000 adapters for Large Language Models, driving demand for efficient multi-adapter serving. All adapters share the same expensive base-model computation, creating a natural opportunity for batching. Existing serverful systems batch across adapters for high throughput but sacrifice per-tenant isolation and elastic scaling. Serverless systems provide both, but at the cost of redundant computation and cross-adapter batching efficiency. We present SwarmLoRA, a disaggregated serverless architecture that resolves this tradeoff by batching shared computation across isolated functions. A persistent aggregator executes a single GEMM for all active requests, while lightweight workers hold only per-adapter state. SwarmLoRA achieves 4.4-5.6x higher throughput than ServerlessLoRA and ServerlessLLM; under trace replay, it completes 98-100% of requests, where baselines complete fewer than one-third. Cold starts take 619 ms (2.9x faster than the fastest baseline) with 95 ms adapter swaps. SwarmLoRA delivers serverful batching efficiency with serverless isolation. Source: Trilce Estrada and Hatem Ltaief, SC26 Papers Co-Chairs