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New generation FPGA announcements do not come often, which makes this a bit exciting for us. Today, Altera is introducing the Agilex 27 as the first family in its new Agilex 2X portfolio. Agilex 27 pairs hardened 800GbE and 1.6TbE Ethernet with PCIe 6.0 and 7.0 support, and offers configurable transceivers up to 256Gbps. What is more exciting, and what I learned on the pre-briefing call, is that Altera also has a new AI-assisted mode for putting these FPGAs to use. HyperFlow and Third-Generation HyperFlex A major new feature of the Agilex 27 family is HyperFlow. HyperFlow is a new full-chip distributed data network that Altera says can move data at multi-terabit-per-second rates throughout the FPGA. That traffic runs on a dedicated network instead of the programmable fabric, so it does not consume soft logic resources or add routing congestion. That leaves more FPGA resources for the application. As an example, a 1.6TbE Ethernet port can bring traffic in through hardened I/O, HyperFlow can carry it across the chip, and the soft logic can spend its resources on processing rather than moving data. The new family has memory controllers for DDR5, LPDDR4, LPDDR5X, and LPDDR6. It also supports UCIe, has crypto acceleration, and Arm Cortex-A720 and Cortex-A520 cores. A trend we have seen in both Altera and Xilinx high-end FPGAs over the past few years is that programmable logic is surrounded by more hardened IP blocks that help bring designs up faster. Ten years ago, the focus was mostly on the programmable logic elements and I/O, but now much more is happening here. Agilex 27 also carries third-generation HyperFlex registers distributed throughout the routing fabric. Altera says Quartus Prime can re-time and pipeline designs through those registers without consuming logic resources. Altera claims a 1.8X generation-over-generation performance-per-watt improvement over Agilex 7 for HyperFlex in Agilex 27. Agilex 27 sits at the high-performance end of the Agilex 2X portfolio, above the mid-range Agilex 25 and the value-optimized Agilex 22 and Agilex 23. Agilex 22 is FPGA-only, while Agilex 23 adds SoC options. QuartusIQ AI Companion QuartusIQ is an AI companion for Quartus Prime that helps developers prioritize steps across compile, timing, debug, and verification. In Altera internal benchmarks comparing Quartus Prime with and without QuartusIQ, design creation was up to 10X faster, and the total design cycle was up to 1.5X faster. The tool integrates with MCP and supports a bring-your-own-key setup. At NVIDIA GTC Berlin 2026, the companies announced that this would be coming to the new RTX Station systems (Windows versions of the DGX Station platforms we have been reviewing at STH). The idea is that you can use QuartusIQ and MCP to design and implement workflows on the chip with local NVIDIA Nemotron as the model. I love this. Final Words The other bit to know about FPGA announcements is that there is generally a big gap between announcement and availability. I asked on the call, and the QuartusIQ bits are this quarter, and the Agilex 27 engineering samples are expected in the second half of 2027. What I really wanted to know is how long it would take to get Agilex 27 and have a local model via MCP build me something like an RDMA-enabled 1.6TbE NIC. My sense is that it will be a 2027 or 2028 timeframe when that happens. It is also something I am super excited about since a barrier to using FPGAs has always been having to know how to program them. At some point, Altera and Xilinx can expand FPGA use if they can deliver AI tools that abstract the hardware platform further. I have a goal of being able to get an FPGA card and have an AI agent implement a NIC or a firewall from scratch on it without having to really get my hands dirty designing the RTL. One day it will happen, and I guess the timeframe is 2027/2028.
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