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AMD introduced AMD Ross, an agentic AI assistant built to run alongside the tools embedded developers already use, from system architecture and schematic review through FPGA and algorithm design, embedded software, AI inference, debugging, and deployment. The assistant targets the whole AMD Embedded portfolio, FPGAs, adaptive SoCs, x86 embedded processors, and edge AI platforms, by connecting a developer’s chosen large language model to AMD’s toolchains through open-standard Model Context Protocol (MCP) servers. The initial release ships with support for the Vivado Design Suite and Vitis HLS, plus AMD’s knowledge base, and AMD is committing to monthly releases from here, a sharp change from the twice-a-year cadence of tools like Vivado. How Ross Connects to the Tools Ross is client-agnostic. AMD’s diagram lists VS Code, Claude Code, Cursor, Devin, and the OpenCode CLI as front ends, and any MCP-compatible client works, with the developer’s preferred LLM, IDE, and command line staying in place. The MCP servers give the AI agents a live connection to the design environment, so an agent can query tool state, run commands, and read results within a session. AMD says permissions remain under the user’s control, with human review gates at the planning and execution steps. Salil Raje, senior vice president and general manager of AMD Embedded, said: “Embedded development is becoming increasingly complex as teams work across hardware design and debug, software development and deployment, AI inference, and system-level design. AMD Ross brings AMD Embedded tools, trusted knowledge, and expert-authored workflows together in a single agentic AI experience grounded in the technologies and methodologies our customers use every day. AMD Ross brings the power of agentic AI to embedded developers to move product innovations from design intent to deployment faster by accelerating the entire life cycle.” At launch, the tool coverage is the Vivado Design Suite for synthesis, place-and-route, and timing closure across the FPGA and adaptive SoC families Vivado supports, and Vitis HLS for compiling C++ algorithms into RTL. In a briefing with StorageReview, Kirk Saban, corporate vice president of product, software, and solutions for AMD’s embedded business, said the three monthly releases planned for the fourth quarter add Power Design Manager for power estimation, ChipScope for in-system hardware debug, and Vitis AI for the AI engines on AMD’s adaptive SoCs, with the schematic and PCB review, x86 embedded, and ROCm pieces of the diagram following through next year. Knowledge Base and Agent Skills Behind the MCP servers sits the AMD Knowledge Base, a set of AMD-validated, vectorized databases of user guides, product guides, white papers, application notes, and answer records that the assistant retrieves against, so a Vivado warning can be matched to the answer record that explains it. The knowledge base runs in the cloud or in a fully offline local deployment, which matters for the aerospace, defense, and functional-safety customers AMD called out; Saban said customers can run Ross on a laptop, a workstation, on-prem GPU servers, or a public cloud, air-gapped with open-weight models if they want, and AMD places no restriction on where it runs. The second layer is Agent Skills, open Markdown files that walk an LLM through a repeatable engineering task: timing closure methodology, RTL linting, dataflow, Vitis HLS loop unrolling, pipelining, and pragma insertion, among others. AMD says more than 20 skills ship in the initial GitHub repository, alongside ready-to-run design examples that show how the skills apply to real hardware, and it expects customers and partners to write their own, keep them private, or contribute them upstream. What AMD Showed, and Who Has Used It Ross has been in early access since the summer, starting with the FPGA tools, and AMD says more than 800 customers are in the program. The demos in the briefing were Vivado-centric: a one-line prompt to create a MicroBlaze-based microcontroller design for a Spartan UltraScale+ evaluation kit produced an 11-step plan and a complete working design, work AMD says takes two to three hours by hand; a single prompt against a post-route design checkpoint classified the timing violations and proposed constraints that, once approved, closed timing on the rerun; and an image sensor pipeline moved from MATLAB through C to RTL in Vitis HLS, where AMD’s HLS skills applied pragmas that cut fabric resource utilization by about 35%. A multi-agent example took a 12-camera pipeline request, generated human- and machine-readable specs, partitioned the work across the x86 CPU, GPU, NPU, and adaptive SoC on a partner board, and compiled the FPGA side in Vivado, with a human approving each stage. These are AMD’s demonstrations and figures; we did not test the assistant. An associate director in iWave Global’s FPGA SOM business unit is quoted in AMD’s materials: “The AMD Ross agentic AI assistant has been a valuable addition to our development workflow. It helps us identify and troubleshoot issues more efficiently, reducing the time and effort required during the debugging and bring-up stages.”
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