Peking University's School of Integrated Circuits has unveiled a prototype EDA tool specifically designed for Huawei's...

Peking University's School of Integrated Circuits has unveiled a prototype EDA tool specifically designed for Huawei's LogicFolding architecture, a 3D chip design approach that folds transistor-level logic into vertical stacks. The tool reportedly achieved a 30% reduction in total wire length in tests, improving performance and thermal management compared to conventional EDA workflows (Tom's Hardware). While this is a university prototype far from production-grade commercial software, it signals growing Chinese capabilities in EDA, a market where Cadence holds a ~30% global share and over 80% in China alongside Synopsys and Siemens. Huawei plans to commercialize LogicFolding in Kirin processors later this year, and if the Peking University tool matures, it could reduce reliance on Western EDA vendors like Cadence and Synopsys. Given the early stage and long development timeline, the threat is not imminent but warrants monitoring. This development is directionally negative for Cadence as it could eventually erode its competitive moat in the Chinese EDA market.